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drp 3510a digital radio processor edition jan. 16, 1997 6251-410-1ai advance information micronas
advance information drp 3510a 2 micronas contents page section title 5 1. introduction 6 1.1. main features 6 1.2. building blocks 6 2. functional description 7 3. specifications 7 3.1. outline dimensions 7 3.2. pin connections and short descriptions 9 3.3. pin descriptions 9 3.3.1. vdd, avdd, vss, avss 9 3.3.2. i 2 cd 9 3.3.3. i 2 cc 9 3.3.4. porq 9 3.3.5. clko 9 3.3.6. xti, xto 9 3.3.7. te 9 3.3.8. pi0..pi3 9 3.3.9. so1c, so1i, so1d 10 3.3.10. si1c, si1d, si1i (adr input interface) 10 3.3.11. spdif 10 3.3.12. so0c, so0i, so0d 10 3.3.13. si1c*, si1d*, si1i* (pi14..16) 10 3.3.14. pi12..pi19 10 3.3.15. eodq, prtwq, pr, (prtrq, pcsq 11 3.4. pin configuration 11 3.5. electrical characteristics 11 3.5.1. absolute maximum ratings 12 3.5.2. recommended operating conditions 13 3.5.3. characteristics 13 3.5.4. recommended crystal characteristics 14 3.5.4.1. single crystal mode ? 24.576 mhz at drp 3510a 14 3.5.4.2. single crystal mode ? 18.432 mhz at msp 3400c 15 3.5.4.3. dual crystal mode ? 18.432/24.576 mhz 16 3.5.4.4. dual crystal mode ? 18.432/18.432 mhz 16 3.5.5. system characteristics 17 4. basic application 18 5. clock concepts 18 5.1. both msp and drp with own crystal running at a 18.432 mhz frequency 18 5.2. msp running with a 18.432 mhz crystal, drp running with a 24.576 mhz crystal 19 5.3. drp running with a 24.576 mhz crystal, msp receives its clock from drp 19 5.4. drp receives its clock from the msp
advance information drp 3510a 3 micronas contents, continued page section title 20 6. interfaces 20 6.1. the adr input interface 20 6.2. the sdo0 interface 21 6.3. the sdo1 interface 21 6.4. the pio interface 21 6.4.1. general purpose pio mode 22 6.4.2. pio-dma mode 22 6.5. the sp/dif interface 22 6.6. copy protection 24 7. the i 2 c interface 24 7.1. the i 2 c-data register 24 7.2. the i 2 c-control register 25 7.3. the i 2 c protocol 25 7.3.1. controller writes to the drp control register 25 7.3.2. controller writes to the drp data register 25 7.3.3. controller reads from the drp data register 26 7.4. the i 2 c commands 26 7.4.1. write into a drp register 26 7.4.2. default read command 27 7.4.3. read from a drp register 27 7.4.4. get adr data 28 7.4.5. write dmx data 28 7.4.6. write data into the d0-memory of the drp 29 7.4.7. write data into the d1-memory of the drp 29 7.4.8. read data from the d0-memory of the drp 30 7.4.9. read data from the d1-memory of the drp 30 7.4.10. freeze 30 7.4.11. the run command 31 8. internal registers and memory areas 31 8.1. default read (index and status) 31 8.2. digital volume and channel mapping (write) 32 9. handling of the drp via internal registers 32 9.1. the internal fixed point number format 33 9.2. main configuration register 96 (write) 34 9.3. agc register 115 (read) 34 9.4. viterbi min-distance register 210 (read) 34 9.5. clock-deviation register 244 (read, write) 34 9.6. timing recovery control register 168 (write) 34 9.7. sp/dif configuration register 83 (write) 34 9.8. sdo0 configuration register 67 (write) 35 9.9. so0auxa register 69 (write) 35 9.10. so0auxb register 70 (write) 35 9.11. sdi1 input configuration register 187 (write) 35 9.12. sdi1 input selection register 79 (write) 35 9.13. actual mpeg header register 117 (read) 36 10. downloading of programs
advance information drp 3510a 4 micronas contents, continued page section title 37 11. application recommendations 37 11.1. msp 3400c parameter setting 37 11.1.1. input gain and differences between the msp 3400c versions c6 and c7 38 11.1.2. mode register 39 11.1.3. fir coefficients for fir_reg1 39 11.1.4. dco increment setting with sat carriers 39 11.2. pure adr music decoding 39 11.3. receiving the adr data 40 11.4. receiving fm / tv sound with msp 40 11.5. receiving of adr 41 11.6. typical adr application circuit (drp application with 24 mhz single crystal mode) 42 11.7. typical adr application circuit (drp application with 18 mhz dual crystal mode) 43 12. timing diagrams 43 12.1. pio timing 43 12.2. fsi timing 44 12.3. sdi timing 44 12.4. sdo timing 44 12.5. spdif timing 45 12.6. recommended power up sequence 45 12.6.1. power up sequence for dual crystal modes 45 12.6.2. power up sequence for 18.432 mhz single crystal mode 45 12.6.3. power up sequence for 24.576 mhz single crystal mode 46 13. drp 3510a version history 48 14. data sheet history
advance information drp 3510a 5 micronas digital radio processor 1. introduction the drp 3510a decodes digital audio data transmitted according to the astra digital radio standard 1) . the drp 3510a has a well-defined interface to the multi- standard sound processor msp 3400c. the drp 3510a and the msp 3400c (alternatively msp 3410d 2) ) provide all functions that are necessary for adr and dmx 3) decoding. the ic is manufactured in a low-cost 0.8 m cmos technology and housed in a 44-pin plcc package. the drp is designed as a coprocessor for the msp, which may already be used in a standard satellite receiv- er. the video baseband a/d converter, the channel selection, some preprocessing of the digital audio sub- carrier, and the tv-sound output are shared with the msp. only those parts that are additionally required for adr-decoding are implemented in the drp. thus, up- grading of existing receiver concepts for adr compati- bility is comparably simple and generates a minimum of additional costs. the core of the digital radio processor is based on the micronas masc dsp. a very important feature of the masc core is its two operating modes: the standard mode that works with 20-bit fixed point numbers and the complex mode that works with 2*10-bit numbers, con- sisting of a10-bit fixed point real part and a 10-bit fixed point imaginary part. this feature offers the opportunity of using the same processor for different tasks like qpsk channel demodulation, mpeg layer 2 source de- coding, and system controlling. consequently, most parts of the adr decoder are implemented as firmware and could easily be updated if required. a special controllable viterbi module has been inte- grated with a burst decoding rate of 2 mbit/s. the data transport between the viterbi module and the dsp is done in the background with an internal non-cycle steal- ing dma. this is exactly the same kind of transport mechanism that is used between the processor core and its various interfaces. the complete data-i/o handling is pushed into the background and does not affect the main processing. fig. 1?1: drp 3510a interfaces sp/dif(0) (iec 958) sdo(0) adr(1) sdo(1) parallel port i 2 c viterbi decoder drp 3510a masc processor core 48 khz 48 khz 32 khz 18.432 mhz or 24.576 mhz 1) astra adr/rev. 1.3 sys ? 078/02 ? 94 tw/ab 15 december 1994 2) msp 3410d is derived from msp 3400c with an added nicam decoding feature. 3) digital music express (for dmx decoding, a verifier-ic and a smartcard reader is additionally required)
advance information drp 3510a 6 micronas 1.1. main features ? single power supply 5 v ? 44-pin plcc plastic package ? on-chip crystal oscillator (18.432 mhz or 24.576 mhz) and internal dco ? general purpose parallel interface ? 1 serial input interface and 2 serial output interfaces i 2 s (32 khz and 48 khz audio out) ? sp/dif output interface (48 khz) ? i 2 c control interface ? download feature for alternative operation modes 1.2. building blocks ? 20-bit masc dsp kernel ? 2-kword internal ram and 6-kword rom (0.75 k config ram) ? qpsk demodulator ? viterbi decoder ? v.35 descrambling ? dmx-descrambler ? mpeg1 layer 2 decoder ? ancillary data processing ? sample rate converter 2. functional description the incoming preprocessed adr-data stream first passes the carrier offset adjustment and the intersymbol interference filtering blocks. then, the sample rate of the signal will be decimated to the symbol rate. a bit slicer is used for the generation of the timing recovery and car- rier offset adjustment control signals. then, the signal is sent to the soft decision viterbi decoder. a linear trans- formation that is placed in front of the viterbi decoder leads to an optimal signal mapping with respect to signal space of the viterbi decoder. the output of the viterbi de- coder is copied to the bit stream buffer of the following mpeg1 layer 2 (musicam) decoder. after the data decompression, the audio signal is avail- able at a sampling frequency of 48 khz at the i 2 s and the sp/dif output interfaces. a third output is used as audio feedback for the msp. for compatibility reasons, a sam- ple rate converter reduces the sampling frequency to 32 khz. in addition to the pure audio signal, some ancillary data are embedded in the mpeg signal. these data are extracted, deinterleaved, error corrected, and sent to the i 2 c interface, where they may be read by the receiver system controller. the software/hardware module that performs a descrambling of pay radio services (in addi- tion to a verifier ic and a ? smart card ? reader) is also con- trolled via the i 2 c bus. fig. 1 ? 2: drp 3510a simplified block diagram channel demod- ulation control dmx output clock control musicam decoder 48 32 khz audio adrin adr-data audio audio sp/dif i 2 s sdo (0) i 2 s sdo(1) 1 48 khz 3 48 khz 3 32 khz 3 2 pio adr(1) i 2 c mpeg pc interface 10
advance information drp 3510a 7 micronas 3. specifications 3.1. outline dimensions 16.5 0.1 4.75 0.15 0.457 10 x 1.27 = 12.7 0.1 10 x 1.27 = 12.7 0.1 1.2 x 45 2.35 2.35 17.4 +0.25 140 39 29 28 18 17 7 6 1.6 1.9 1.5 4.05 16.5 0.1 0.1 17.4 +0.25 5 8.6 6 2 2 x 45 1 +0.2 1.27 0.1 1.27 0.1 fig. 3 ? 1: 44-pin plastic leaded chip carrier package (plcc44) weight approximately 2.5 g dimensions in mm 0.711 0.254 0.05 3.2. pin connections and short descriptions nc = not connected; leave vacant lv = if not used, leave vacant x = obligatory; connect as described in circuit diagram vdd_10k = connected with vdd via 10 k resistor vss_10k = connected with vss via 10 k resistor pin no. connection pin name type short description plcc 44-pin (if not used) 1 x vss supply digital ground 2 x vdd supply 4.75 to 5.25 v power supply 3 lv i 2 cd in/out i 2 c-data line 4 vdd i 2 cc in/out i 2 c-clock line (must be set to vdd on reset) 5 x porq in reset active low 6 lv clko out clock out 7 x avss supply 0 v for analog circuits 8 x xti in crystal input (18.432 or 24.576 mhz) base mode, clock input 9 x avdd supply 4.75 to 5.25 v for analog circuits 10 lv xto out crystal oscillator output 11 vss te in test enable 12 nc
advance information drp 3510a 8 micronas short description type pin name connection pin no. (if not used) plcc 44-pin 13 x pi0 in pio data [0] crystal select. 0: 18.432 mhz, 1: 24.576 mhz; should be con- nected with vss (vdd) via a resistor (e.g. 10 k) 14 vss_10k pi1 in pio data [1] reserved task input; should be connected with vss via resistors (10k) 15 vss_10k pi2 in pio data [2] reserved task input; should be connected with vss via resistors (10k) 16 x pi3 in pio data [3] 0: adr-mode, 1: layer 2 decoder; should be connected with vss (vdd) via a resistor (e.g. 10 k) 17 x so1c in/out clock of the sdo1 interface, 32 khz audio out 18 x so1i out frame indication of the sdo1 interface, 32 khz audio out 19 x so1d out data of the sdo1 interface, 32 khz audio out 20 x si1c in/out clock of the sdi1 interface, 384 khz clock of adr data 21 x si1i in frame indication of the sdi1 interface, (i/o of adr data) 22 x si1d in data of the sdi1 interface, adr input data 23 x vss supply digital ground 24 x vdd supply 4.75 to 5.25 v power supply 25 nc 26 lv spdif out sony philips digital interface, 48 khz stereo audio 27 lv so0c in/out clock of the sdo0 interface, 48 khz audio out 28 lv so0i out frame indication of the sdo0 interface, 48 khz audio out 29 lv so0d out data of the sdo0 interface, 48 khz audio out 30 lv pi12 (in/out) pio data [12] in/out 31 lv pi13 (in/out) pio data [13] in/out 32 vss_10k pi14 (si1d*) (in/out) i pio data [14] (alternative input for si1d) 33 vss_10k pi15 (si1i*) (in/out) i pio data [15] (alternative input for si1i) 34 nc 35 vss_10k pi16 (si1c*) (in/out) i pio data [16] (alternative input for si1c) 36 lv pi17 (in/out) o pio data [17] (not used)
advance information drp 3510a 9 micronas short description type pin name connection pin no. (if not used) plcc 44-pin 37 lv pi18 (crce) (in/out) o pio data [18] (crc-error) 38 lv pi19 (fsi ) (in/out) o pio data [19] (frame start impulse, low active) 39 vdd_10k pcsq in pio chip select 40 vdd_10k pr in pio read/write 41 lv prtwq out pio ready to write 42 lv prtrq out pio ready to read 43 lv eodq out pio end of dma 44 nc 3.3. pin descriptions 3.3.1. vdd, avdd, vss, avss vdd and avdd should be blocked against vss and avss. for proper operation and in order to avoid emv problems, a capacitive blocking of vdd against vss over a wide frequency range is recommended. 3.3.2. i 2 cd the i 2 cd line is used for i 2 c data transfers from the drp to a controller and vice versa. 3.3.3. i 2 cc the i 2 c clock line is used for the i 2 c clock if the ic is in the operation mode. however, on a power on reset, the i 2 c line determines the operating mode of the internal clock generator of the drp. if the i 2 cc line is set to low during power on reset, the internal drp clock is directly taken from the crystal input xti and the internal crystal oscillator is disabled. in standard adr mode, the i 2 c clock pin has to set to high level, in order to activate the internal oscillator and the internal dco, which is used to synchronize the drp clock system with the data rate of the incoming adr signal. 3.3.4. porq reset input (active low). the minimum length of a reset impulse should be 100 s. see the timing diagrams (sec- tion 12.) for the recommended power up sequence and further details. 3.3.5. clko if the drpa is driven with a 24.576 mhz quartz, the clko pin delivers a synchronized 18.432 mhz clock, otherwise the the clko pin is muted. 3.3.6. xti, xto the crystal input xti can either be used for the crystal application or for a direct input of a clock signal with the correct frequency. if the xti signal is used for direct in- put, the input signal has to be dc-free, a minimum level of 0.7 v ss and a maximum level of 3 v ss .the xto signal is the output of the internal crystal oscillator. 3.3.7. te the te pin is reserved for chip testing only. for customer applications, this pin must always be connected to vss. 3.3.8. pi0..pi3 in standard pio mode, these pins are static input pins that allow the selection of different operating modes. the pi0 pin is used to select the used crystal frequency. the level of the pi0 pin is evaluated within 10 ms after reset. the pi3 pin is used to select the basic operating mode (either adr or l2-only decoding). the pi1 and pi2 inputs are reserved for future use and have to be set to ? 0 ? . because these pix pins are generally used as input pins, it is recommended to connect them with a fixed po- tential. however, in dma output mode, they operate as output pins. thus, their connection with vss or vdd should be done via 10 k resistors in order to avoid short- circuits. 3.3.9. so1c, so1i, so1d these three serial data output lines transport the de- coded adr/dmx signal at a sample rate of 32 khz. an
advance information drp 3510a 10 micronas internal sample rate converter performs the 48 to 32 khz downsampling. for proper adr-operation, it is manda- tory to connect them with one i 2 s input of the msp. the msp clock system has to be switched into ? slave mode ? . the data word is not delayed vs. the word-strobe (so1i) signal. 3.3.10. si1c, si1d, si1i (adr input interface) the adr input interface has to be connected with the adr/s-bus interface of the msp chip. in layer 2 mode, the lines si1c (for clock) and si1d (for data) will expect a valid layer 2 data stream. 3.3.11. spdif the spdif interface provides the adr/dmx data in the digital spdif format, in accordance with the consumer standard iec 958. 3.3.12. so0c, so0i, so0d the so0 output interface is the standard interface for a 48 khz additional dac, for full sampling rate output, which is not implemented in the msp. the data word is not delayed vs. the word-strobe (so1i) signal by default. 3.3.13. si1c * , si1d * , si1i * (pi14..16) these lines are used as alternative input lines and could be connected e.g. with the i 2 s output of the msp. how- ever, these input pins are not supported by the built-in firmware. downloaded program codes can use these in- put lines for alternative functionality of the drp. an ex- ample for an adequate download program is an i 2 s to sp/dif converter program that can be used to map the analog fm-sound signal from the msp to the sp/dif output interface of the drp. in the standard adr-mode, these lines are input pins that should be connected via resistors to a fixed level (vss). 3.3.14. pi12..pi19 in standard adr mode, the pio pin pi19 shows the frame start impulse (fsi). this impulse is synchronized with the mpeg frame and is set to low level for at maxi- mum 23 ms, which indicates that a new adr ancillary data block is available for read-out via i 2 c. the crc-er- ror pin pi18 will be set to high level for 24 ms (duration of one mpeg layer 2 frame) when an mpeg crc error has been detected. in dma mode, the pi12..pi19 pins will contain the 8-bit aligned undecoded mpeg data stream. 3.3.15. eodq, prtwq, pr, (prtrq, pcsq) for a description of eodq, prtrq, pr, see section 6.4.2. the prtrq line is reserved for future use. the pcsq line is not used by the actual firmware and should be connected to vdd via a resistor.
advance information drp 3510a 11 micronas 3.4. pin configuration 7 8 9 10 11 12 13 14 15 16 17 29 30 31 32 33 34 35 36 37 38 39 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 drp 3510a top view pcsq pi19 (fsi ) pi18 (crce) pi17 pi16 (si1c*) nc pi15 (si1i*) pi14 (si1d*) pi13 pi12 so0d so0i so0c spdif n.c. vdd vss prtwq prtrq eodq nc vss vdd i2cc porq pi0 pi2 pi3 so1c pi1 te xto avdd xti avss clko so1i so1d si1c si1i si1d i2cd nc pr fig. 3 ? 2: 44-pin plcc package 3.5. electrical characteristics 3.5.1. absolute maximum ratings symbol parameter pin no. min. max. unit t a ambient operating temperature ? ? 20 85 c t s storage temperature ? ? 40 125 c v sup supply voltage 2, 9, 24 ? 0.2 6 v v pin pin voltage all other pins ? 0.3 v sup +0.3 or 6 whatever is less v c l load capacitance all out p ut 0 200 pf r l load resistance to v sup or gnd out ut pins 500 1) infinite ? i l load current open drain outputs 3, 4 10 ma 1) shorts will not damage the ic, if they do not exceed a time period of 5 s stresses beyond those listed in the ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the ? recommended operating conditions/characteristics ? of this specification is not implied. exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability.
advance information drp 3510a 12 micronas 3.5.2. recommended operating conditions at v sup = 4.75 to 5.25 v symbol parameter pin no. min. typ. max. unit t a ambient operating temperature ? 0 65 c v sup supply voltage 2, 9, 24 4.75 ? 5.25 v f cp internal processor clock frequency (set by software) ? 40 mhz v dil data input low voltage all other inputs ? 1 v v dih data input high voltage i npu t s v sup ? 1 ? v t res reset input low time (after v sup has reached specified range) 5 20 ms t pic pio timing (see fig. 12 ? 1) 13 ? 22, 28 4 3 50 no limit ns t pip pio timing (see fig. 12 ? 1) 28 ? 43 0 no limit ns t pir pio timing (see fig. 12 ? 1) 0 no limit ns t piset pio timing (see fig. 12 ? 1) 50 no limit ns t pihold pio timing (see fig. 12 ? 1) 50 no limit ns t sisclk sdi timing (see fig. 12 ? 3) 20 ? 22, (32 33 120 ns t siiss sdi timing (see fig. 12 ? 3) (32 , 33 , 35) 30 ns t siids sdi timing (see fig. 12 ? 3) 30 ns t siish sdi timing (see fig. 12 ? 3) 30 ns t siidh sdi timing (see fig. 12 ? 3) 30 ns t siilia sdi timing (see fig. 12 ? 3) 480 no limit ns t sosclk sdo timing (see fig. 12 ? 4) 17, 27 120 ns v i2icil i 2 c-bus input low voltage 3, 4 0.3 v sup v i2icih i 2 c-bus input high voltage 0.6 v sup t i2c1 i 2 c-start condition setup time 120 ns t i2c2 i 2 c-stop condition setup time 120 ns t i2c3 i 2 c-clock low pulse time 500 ns t i2c4 i 2 c-clock high pulse time 500 ns t i2c5 i 2 c-data setup time before rising edge of clock 55 ns t i2c6 i 2 c-data hold time after falling edge of clock 55 ns f i2cih i 2 c-bus frequency 1.0 mhz
advance information drp 3510a 13 micronas 3.5.3. characteristics at v sup = 4.75 to 5.25 v, t amb = 0 to 65 c symbol parameter pin no. min. typ. max. unit test conditions p power consumption 900 1100 mw at 40 mhz c l = 30 pf on all outputs v dol data output low voltage 1) 0.6 v i load = 10 a t fall data output high to low transition time 2) 10 ns c l = 50 pf max. v doh data output high voltage 1) v sup ? 0.6 v i load = ? 10 a t rise data output high to low transition time 1) 10 ns c l = 50 pf max. v doli i 2 c output low voltage, i 2 c switching hysteresis on por 3, 4 0.4 0.6 v v i load = 3 ma i load = 6 ma i dohi i 2 c output high leakage current 0 2 a v doh = 5 v v reshys hysteresis voltage of por 5 160 240 320 mv t piw pio timing (see fig. 12 ? 1) 13 ? 22, 28 4 3 0 ns t pie pio timing (see fig. 12 ? 1) 28 ? 43 ? 25 0 25 ns equal load capacitance on eod , rtr , and rtw t pieset pio timing (see fig. 12 ? 1) 50 ns c l = 50 pf max. t pihold pio timing (see fig. 12 ? 1) 50 ns c l = 5 pf min. t fsiv fsi timing, (see fig. 12 ? 2) 38 22 23 ms c l = 5 pf min. t fsip fsi timing, (see fig. 12 ? 2) 23 24 25 ms c l = 5 pf min. t sosclk sdo timing (see fig. 12 ? 4) 17 ? 19, 27 2 9 120 ns t soiss sdo timing (see fig. 12 ? 4) 27 ? 29 10 ns t soodc sdo timing (see fig. 12 ? 4) 10 ns t spclk spdif timing (see fig. 12 ? 5) 325 ns 1) all other output and input/output pins except 3 and 4 2) all output and input/output pins 3.5.4. recommended crystal characteristics symbol parameter pin no. min. typ. max. unit v xca external clock amplitude 8 0.7 v pp t jitter clock jitter without timing recovery control 2 ns
advance information drp 3510a 14 micronas 3.5.4.1. single crystal mode ? 24.576 mhz at drp 3510a symbol parameter pin no. min. typ. max. unit f p parallel resonance frequency at 12 pf load capacitance 24.576 mhz f tol accuracy of adjustment ? 100 +100 ppm d tem frequency variation versus temperature ? 50 +50 ppm r r series resistance 20 ? c 0 shunt (parallel) capacitance 7.0 pf load capacitance recommendations c l external load capacitance *) 8, 10 18 pf f cl required open loop clock frequency (t amb = 25 c) 24.574 24.576 24.578 mhz *) remark on defining the external load capacitance: external capacitors at each crystal pin to ground are required. they are necessary to tune the free running frequen- cy of the drp or the open-loop frequency of the msp. the higher the capacitors, the lower the clock frequency re- sults. the nominal free running frequency should match 18.432/24.576 mhz as closely as possible. due to different layouts of customer pcbs the matching capacitor size should be defined in the application. the suggested values are figures based on experience with various pcb layouts. for adjusting the drp crystal frequency, use external capacitors with 5% tolerance. 3.5.4.2. single crystal mode ? 18.432 mhz at msp 3400c symbol parameter pin no. min. typ. max. unit f p parallel resonance frequency at 12 pf load capacitance 18.432 mhz f tol accuracy of adjustment ? 30 +30 ppm d tem frequency variation versus temperature ? 30 +30 ppm r r series resistance 8 25 ? c 0 shunt (parallel) capacitance 6.2 7.0 pf c 1 motional (dynamic) capacitance 15 ff load capacitance recommendations c l external load capacitance *) 8, 10 3.3 pf f cl required open loop clock frequency (t amb = 25 c) 18.4305 18.432 18.4335 mhz
advance information drp 3510a 15 micronas 3.5.4.3. dual crystal mode ? 18.432/24.576 mhz symbol parameter pin no. min. typ. max. unit for msp f p parallel resonance frequency at 12 pf load capacitance 18.432 mhz f tol accuracy of adjustment ? 20 +20 ppm d tem frequency variation versus temperature ? 20 +20 ppm r r series resistance 8 25 ? c 0 shunt (parallel) capacitance 6.2 7.0 pf c 1 motional (dynamic) capacitance 19 24 ff load capacitance recommendations c l external load capacitance *) 8, 10 3.3 pf f cl required open loop clock frequency (t amb = 25 c) 18.431 18.432 18.433 mhz for drp f p parallel resonance frequency at 12 pf load capacitance 24.576 mhz f tol accuracy of adjustment ? 20 +20 ppm d tem frequency variation versus temperature ? 20 +20 ppm r r series resistance 20 ? c 0 shunt (parallel) capacitance 7.0 pf load capacitance recommendations c l external load capacitance *) 8, 10 18 pf f cl required open loop clock frequency (t amb = 25 c) 24.5747 24.576 24.5773 mhz
advance information drp 3510a 16 micronas 3.5.4.4. dual crystal mode ? 18.432/18.432 mhz symbol parameter pin no. min. typ. max. unit f p parallel resonance frequency at 12 pf load capacitance 18.432 mhz f tol accuracy of adjustment ? 20 +20 ppm d tem frequency variation versus temperature ? 20 +20 ppm r r series resistance 8 25 ? c 0 shunt (parallel) capacitance 6.2 7.0 pf c 1 motional (dynamic) capacitance (at msp, not required at drp) 19 24 ff load capacitance recommendations c l external load capacitance *) 8, 10 msp: 3.3 drp: 18 pf pf f cl required open loop clock frequency (t amb = 25 c) 18.431 18.432 18.433 mhz 3.5.5. system characteristics symbol parameter min. typ. max. unit f r covered frequency range for receiving 0.180 9.00 mhz c/n clear c/n for error rate < 1*10 ? 5 9.5 db c/n aqu c/n for acquisition 8.5 db t rec lock time 0.2 s f lockrange carrier lock range ? 2.0 +2.0 khz
advance information drp 3510a 17 micronas 4. basic application the adr decoder application shows the obligatory parts: msp 3400c and drp 3510a. in full transponder mode (48 adr-channels on one transponder), the tuner output signal should be directly connected with the msp. in standard mode, the video signal should be sup- pressed with a highpass filter. the two analog inputs of the msp can be used for selecting either full-transpond- er or standard mode. the built-in d/a converter of the msp generates the analog audio output. optionally, a 48 khz d/a converter may be connected to the second i 2 s output interface. the system controlling is done via the i 2 c interface. tuner drp 3510a 0...9 mhz baseband msp 3400c d/a 32 khz sp/dif (iec 958) digital out at 48 (32) khz i 2 s adr-interface fig. 4 ? 1: adr/dmx decoder application i 2 c-bus high quality d/a converter 48 khz smartcard reader analog out (stereo) a/d dmx verifier system controller (e.g. ccu 3000) a/d sdi1 sdo1 sdo0 sp/dif video filter i 2 s2-data (for future use) i 2 s to sp/dif sdi1*
advance information drp 3510a 18 micronas 5. clock concepts in order to support various applications and board lay- outs, different clock concepts are supported. each of the described clock concepts has its advantages. the digital nature of the adr bit stream forces the decoder ic to synchronize its clock frequency to the symbol rate of the incoming signal. both the msp and the drp clock have to be synchronized, but only the drp does the timing re- covery. the msp clock is synchronized indirectly with a pll that locks onto the i 2 s (so1) signal from the drp. thus, the i 2 s feedback connection is mandatory in all adr applications. see the application recommenda- tions (section 11.) for further details. 5.1. both msp and drp with own crystal running at a 18.432 mhz frequency the ? two crystal mode ? is the standard application for the adr-chip set. two identical crystals may be used. this mode is preferable in all applications where a consider- able physical distance between both ics is given by the actual board layout. fig. 5 ? 1: two crystal mode 18.432 mhz adr-bus i 2 s msp 3400c drp 3510a dac 48 khz aud_cl_out 18.432 mhz so0 so1 si1 (18.432 mhz) pi0 gnd 10 k 5.2. msp running with a 18.432 mhz crystal, drp running with a 24.576 mhz crystal the ? two crystal mode ? with a 18.432 and a 24.576 mhz crystal leads to a smaller power dissipation (about 10% smaller) for the drp and makes it possible to derive the oversampling clock for the optional 48 khz dac directly from the drp (position ii of the switch in fig. 5 ? 2). fig. 5 ? 2: two crystal mode with 18.432 and 24.576 mhz crystal 18.432 mhz adr-bus i 2 s msp 3400c drp 3510a dac 48 khz aud_cl_out 24.576 mhz so0 so1 si1 (18.432 mhz) pi0 +5 v 10 k 18.432 mhz clko 18.432 mhz i ii table 5 ? 1: clock concepts clock concept 5.1. 5.2. (i/ii) 5.3. 5.4. processor clock 39.936 mhz 36.864 mhz 36.864 mhz 39.936 mhz timing recovery control register (see 9.6.) no action required no action required no action required $200 comment less power consumption msp crystal is omitted, best c/n, low crystal spec., less power con- sumption 4-bit dac (48 khz) is required
advance information drp 3510a 19 micronas 5.3. drp running with a 24.576 mhz crystal, msp re- ceives its clock from drp in this ? single crystal mode ? , the msp clock is taken from the drp. this avoids any problems that may arise due to frequency deviations of the crystals. the drp-pll works directly without any effects caused by the msp. so the best c/n performance can be reached. the 24.576 mhz crystal leads to a smaller power dissipation (about 10% smaller) for the drp. this is the most cost effective solution, because the crystal specification is very low. the oversampling clock for the optional 48 khz dac comes directly from the drp. the nicam mode of the msp 3410d is not useable. if the system in this mode is running without an adr-carrier at the input, the clock will slowly drift to its maximum deviation. the drp clock can be restored either to its default value by writing the value ? 0 ? into the clock-deviation register (see 9.5.) or better with an initialization value according to section 11.5. af- ter a simultaneous hardware reset of msp and drp, it is necessary to give the msp a software reset using an i 2 c-command. a msp software reset (via i 2 c) is neces- sary after each reset (by hardware or by i 2 c) of the drp. fig. 5 ? 3: single-crystal mode with 24.576 mhz adr-bus i 2 s msp 3400c drp 3510a dac 48 khz xtal_in 24.576 mhz so0 so1 si1 (18.432 mhz) pi0 +5 v 10 k clko 10 nf 5.4. drp receives its clock from the msp in this ? single crystal mode ? , the drp clock is taken from the msp. this avoids any problems that may arise due to frequency deviations of the crystals. however, this mode leads to a more critical symbol-clock recovery. the reference clock of the drp is generated by the msp, which again is the base for the drp system. this causes an integrating system behavior that has to be stabilized by changing some control circuit parameters (write $200 into timing recovery control register ? see 9.6.). if the system in this mode is running without an adr-carrier at the input, the clock will slowly drift to its maximum devi- ation. the drp clock can be restored either to its default value by writing the value ? 0 ? into the clock-deviation reg- ister (see 9.5.) or better with an initialization value ac- cording to section 11.5. fig. 5 ? 4: single crystal mode with 18.432 mhz 18.432 mhz adr- bus i 2 s msp 3400c drp 3510a dac 48 khz aud_cl_out so0 so1 si1 (18.432 mhz) pi0 gnd 10 k 10 nf xti
advance information drp 3510a 20 micronas 6. interfaces 6.1. the adr input interface the adr input lines si1c, si1d, and si1i are designed as a direct interface to the msp. these lines transport some preprocessed channel-data from the msp, which are directly used for the channel decoding within the drp (see the msp 3400c/d data sheet for connecting the msp with the drp). if the layer 2 mode is selected, the adr interface expects layer 2 data instead of adr data. the format for the l2 data stream is shown in fig. 6 ? 1. short interruptions of the data stream are al- lowed (< 5 ms). however, the mean input data rate must correspond to the data rate that is coded in the mpeg bit stream. it is possible to route the input to sdi1* by us- ing the input selection register (see 9.12.). 6.2. the sdo0 interface the sdo0 interface passes the decoded 48 khz audio signal e.g. to a high quality d/a converter. the serial for- mat generates 2*32 bits for stereo audio samples on the data line so0d, a word strobe so0i, and a serial clock at the so0c line. the first 18 bits of each mono-sample contain valid data, bit 19 and bit 20 are always set to zero. the 12 trailing bits are determined by the content of the so0auxa (left) and so0auxb (right) registers. some high quality dacs do need an oversampled clock signal. if the drp is working with a 24.576 mhz crystal, the oversampled clock may be taken from the clkout pin of the drp. if working with a 18.432 mhz crystal, the oversampled clock has to be taken from the msp-clock- out. in the 18.432 mhz msp single crystal mode, the ex- ternal dac should not be a 1-bit converter. this is to pre- vent clock jitter effects caused by the timing recovery. si1c si1d si1i low high low high low high interrupt of data flow fig. 6 ? 1: schematic timing of a mpeg layer2 input data stream so0c so0i so0d low high low high low high left 1 right 1 left 2 right 2 00 31 31 fig. 6 ? 2: schematic timing of the sdo0 output interface
advance information drp 3510a 21 micronas 6.3. the sdo1 interface the sdo1 interface sends a decoded 32 khz audio sig- nal back to the msp. the 32 khz signal is generated via an internal high quality sample rate converter, which is perfectly matched to the performance of the msp dacs. the cutoff frequency now is reduced to approximately 15 khz. the signal of most of the free to air adr-sta- tions, however, does not exceed this cutoff frequency. the serial format generates 2*16 bits for stereo audio samples on the data line so1d, a word strobe on the so1i, and a serial clock at the so1c line. this offers the opportunity to use the mspc dacs for analog output. this connection to the mspc is obligatory for every ap- plication, even if it is not intended to use the mspc dacs. this is due to the fact that the clock synchroniza- tion between drp and msp uses this connection. the timing of the sdo1 interface is shown in fig. 6 ? 3. 6.4. the pio interface the pio interface can be used in two different modes. in the standard mode, the pio lines pi0..pi3 are used to select the crystal frequency or to switch between differ- ent applications; and the pi12..pi19 lines are used as signalling outputs or serial interface pins (see section 3.2.). in a second mode, the dma mode (direct memory access), the internal mpeg layer 2 data stream (after descrambling but before decoding) is provided on the pio lines pi12..pi19. 6.4.1. general purpose pio mode the general purpose pio mode is selected after reset. in this mode, the pio-lines have the functionality as de- scribed below. the pi0 and pi3 pins are only read out af- ter a reset of the drp. so0c so0i so0d low high low high low high left 1 right 1 left 2 right 2 00 15 15 fig. 6 ? 3: schematic timing of the sdo1 output interface table 6 ? 1: functionality of the pio mode pi0 pi1 pi2 pi3 pi14 pi15 pi16 pi18 pi19 crystal select mode select si1d* si1i* si1c* crce fsi (def. mode) 0 18.432 adr alternative input lines (for example: i 2 s to sp/dif con- version in combination with no crc error anc.data available 1 24.576 l2 de- coder vers i on i n com bi na ti on w ith downloaded software) crc error anc.data invalid
advance information drp 3510a 22 micronas 6.4.2. pio-dma mode the pio-dma mode is selected by setting the corre- sponding bit in the main configuration register 96. the pio-dma mode gives access to the undecoded data, which are simultaneously sent to the integrated mpeg layer 2 decoder. in this mode, pio lines pi0..pi3 and pi12..pi19 are switched to output. the pio lines pi12..pi19 will give an 8-bit parallel access to the bit stream data. the data is always sent in packets of 16 by- tes every 0.667 ms. the data are 8-bit aligned with msb first (at position pi19). the mpeg data are aligned in such a way that the first bit of the mpeg header is always positioned at the msb (pi19) of the 8-bit word. in order to read out the data stream, a special handshake proto- col must be used (see fig. 6 ? 4). the data transfer is started after the eodq-pin of the drp is set to an active state. after checking this, the con- troller requests data by activating the pr-line. the drp asserts that the first data word is placed on the bus by generating a negative strobe impulse on prtw . now, the controller may read the data word, and subsequent- ly, it may request the next byte by activating the pr-line again. this procedure will be repeated 16 times. after the 17th pr impulse of the controller, the eodq signal of the drp will be activated, which indicates that the transfer of one data block has been finalized. the data for one 16-byte block is transmitted in 0.6 ms. however, the complete protocol should be executed in less than 0.5 ms to avoid data loss. a description of timing details can be found in section 12.1. this pio-dma mode will not work in the e4 version (see also section 13). 6.5. the sp/dif interface the sp/dif interface generates a 48, 44.1, or 32 khz digital signal conforming to the iec 958 consumer stan- dard. in adr mode, only 48 khz sampling frequencies are generated. the interface definition covers the data stream and the physical timing specifications of the data transmission. the transmission is done via the ? bi- phase-mark ? code (fig. 6 ? 5). the sp/dif signal consists of 32-bit subframes. the first 4 bits are used for the sync impulse (preambles). there are three different sync signals: the first subframe nor- mally starts with preamble ? x ? . however, the preamble changes to preamble ? z ? once every 192 frames. ? z ? also indicates the block begin, which is used to organize the channel status information. the second subframe al- ways starts with preamble ? y ? . (see fig 6 ? 7). two sub- frames form one frame, 192 frames are collected into one super-frame (or block). the preamble is followed by 4 auxiliary bits, which are not used in this application (forced to 0), and 20 data bits. a subframe will be com- pleted with the validity bit, user bit, channel status bit, and parity bit (see fig 6 ? 6). 6.6. copy protection the copy protection mode is set either according to the incoming mpeg bit stream or explicitly to ? no copy al- lowed ? regardless of the copy protection setting of the mpeg bit stream. the copy protection mode is select- able by setting bit 8 in the main configuration register. in the default mode (bit 8 = 0), the copy bit of the mpeg bit stream that is set by the service provider is directly eva- luated to set the copy protection within the spdif output bit stream. if copy protection is coded in the mpeg header, one can record the program, but a further digital copy of the recorded material is not allowed. if no copy protection is coded in the mpeg header, a digital copy is allowed. the copy protection can be forced regardless of the copy protection setting in the mpeg bit stream by setting the main configuration register (bit 8 = 1). eodq low high pr prtw pi12...19 low high low high low high fig. 6 ? 4: handshake protocol for getting mpeg data via pio-dma
advance information drp 3510a 23 micronas 0 18 29 10 3 411 512 613 7 1 001 0 1 1 data bit stream (example) biphase-mark code with z-preamble biphase-mark code with x-preamble biphase-mark code with y-preamble preamble = sync-impulse data bit number 31 fig. 6 ? 5: preamble and biphase-mark code specification (polarity may be changed) preamble 0347 00 0 0 8 20-bit audio sample word lsb msb 27 28 29 30 31 validity bit user data bit channel status bit parity bit fig. 6 ? 6: subframe format channel1 channel1 channel1 channel2 channel2 channel2 xy y y xx z subframe 2 subframe 1 frame 0 frame 1 frame 191 start of block fig. 6 ? 7: frame format
advance information drp 3510a 24 micronas 7. the i 2 c interface i2cc i2cd i 2 c-control (to task and reset) i 2 c-data register iic-slave-decoder device address: 1101010x ($d4 (dev_write), $d5 dev_read)) slave-subaddresses: 01101000 ($68) 01101001 ($69) 01101010 ($6a) control subaddress read subaddress write i 2 c lines (must be connected with vdd on drp reset) fig. 7 ? 1: schematic diagram of the i 2 c-bus-interface of the drp 7.1. the i 2 c-data register the i 2 c-data register is used to communicate with the internal firmware of the drp. it has a length of 16 bits. the data transfer is done with the msb first. the follow- ing table shows the bit assignment used in this docu- ment. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb 7.2. the i 2 c-control register the i 2 c-control register is used to set the tasks to switch between different operating modes and to gener- ate a hardware reset. if the reset bit is set to ? 1 ? , the drp will stay in the ? reset ? state. this i 2 c reset will affect all blocks of the drp but not the i 2 c-interface itself. thus, writing a new word into the control register with the reset bit 8 cleared, will restart the processor. if the task bits t0...t3 are set, the corre- sponding tasks in the drp are set permanently. the bits c4...c7 must always be set to ? 0 ? . if no bit is set, the drp will work in its default mode, which is adr-decoding. task 3 corresponds to the layer 2 only decoder. c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 reserved bits re- set 0 0 0 0 t3 t2 t1 t0
advance information drp 3510a 25 micronas 7.3. the i 2 c protocol a data transfer via i 2 c is always initiated by an external controller with a start condition on the i 2 c bus. then, the controller sends the device address and the subad- dress. the value of the subaddress specifies the direc- tion of the following data transfer. the subaddresses $68 and $6a indicate a transfer from the controller to the drp, the subaddress $69 indicates a transfer from the drp to the controller. the transfer is continued until a stop condition is transmitted by the controller. sda scl 1 0 sp w=0 r=1 a=0 nak = 1 fig. 7 ? 2: timing of start (s) and stop (p) condition of the i 2 c protocol 7.3.1. controller writes to the drp control register s dev_write ($d4) a control_adr ($6a) a control_high (8) a control_low (8) a p fig. 7 ? 3: writing a control word into the control register 7.3.2. controller writes to the drp data register s dev_write ($d4) a data_write ($68) a data_high (8) a data_low (8) a p fig. 7 ? 4: writing a 16-bit word into the data register 7.3.3. controller reads from the drp data register s a data_read ($69) a data_high (8) a data_low (8) a p dev_write ($d4) s nak (last transfer) may be repeated a dev_read ($d5) fig. 7 ? 5: reading 16-bit data word(s) from the data register
advance information drp 3510a 26 micronas 7.4. the i 2 c commands the following commands are used to communicate with the drp-firmware. the commands are executed by the drp during the normal operation without any interrup- tions of the audio signal. these i 2 c commands do allow an external system controller to access all internal states, ram contents, and even the internal hardware control registers. this may be very useful for special pur- pose application and non standard operation modes. note: writing values into not documented internal drp registers or ram-cells may corrupt the decoding pro- cess and may lead to unpredictable processor states, which can be left only by a hardware reset of the whole system. the description of the various i 2 c commands uses the following formalism: a value is split into nibbles, which are numbered beginning with 0 for the least significant nibble. the data values or the nibbles are written in hexadecimal notation indicated by a preceding $ char- acter. a hexadecimal number is written, for example, as d=$17c63. the 5 nibbles of this number are d0=$3, d1=$6, d2=$c, d3=$7, d4=$1. register addresses are called r , data values are called d , addresses a, and a count value is called n . if a fixed number is to be used, it is listed directly preceded by a $-sign. 7.4.1. write into a drp register s dev_write ($d4) a data_write ($68) a $9 r1 a r0 d0 d4 d3 a d2 d1 a p a fig. 7 ? 6: write a 20-bit value d =(d4,d3,d2,d1,d0) into register r = (r1,r0) the drp has an address space of 256 registers, 128 of them in the d0-area and 128 in the d1-area. some of the registers are direct control inputs for various hardware blocks, others do control the internal program flow. in the next section, those registers that may be changed by the system controller are described in detail. ? writing random values into undocumented registers may corrupt the execution of the program. 7.4.2. default read command s a data_read ($69) a status a index nak p dev_write ($d4) s a dev_read ($d5) fig. 7 ? 7: default read of a 16-bit word ( status and index ) from the drp the status and index values are described in section 8.1.
advance information drp 3510a 27 micronas 7.4.3. read from a drp register 1. send command 2. get register value s dev_write ($d4) a data_write ($68) a $d r1 a r0 $0 a p s dev_write ($d4) a data_read ($69) a d3 d2 a d1 d0 $xx a $x d4 nak p a a dev_read ($d5) s fig. 7 ? 8: reading a 20-bit value from a drp register 7.4.4. get adr data 1. send command 2. get data s dev_write ($d4) a data_write ($68) a $60 a offset count a p s dev_write ($d4) a data_read ($69) a status a index adr0 a adr1 a a dev_read ($d5) adr2 a adr3 a adr4 a adr5 a a a adr7 adr8 a adr9 a adr10 a adr11 a adr12 a adr13 a adr6 a adr14 a adr15 (ctrl 0) a adr16 (ctrl 1) a adr17 (ctrl 2) nak p a fig. 7 ? 9: reading the status, index, and the 18 bytes of adr-data from the drp s offset: first value to be read ($0...$9) count: number of words to be read ($1...$a) read the complete data field: offset = 0, count = $a read only control data: offset = 8, count = 2 the 18 bytes of the adr data will be updated every 24 ms. the content of this data field is documented in the adr-specification. these data are already deinter- leaved and error corrected. the last three bytes do al- ways keep the control data. the meaning of the first 15 bytes may change due to different services. in order to optimize the access to the adr data, a simple selection mechanism has been implemented where the offset and the number of word to be read could be selected. it is im- portant that this command is always completed, i.e. the number of words passed by ? count ? to the drp has to be read by the controller, otherwise the operation sys- tem may crash. the msb of control byte 1, which indi- cates that the auxiliary and rds data in the frame are complemented, will be processed internally according to the ? free to air ? standard. thus, this bit is always set to
advance information drp 3510a 28 micronas zero, indicating that the inversion of the control data must not be done by the controller. in case of dmx, the meaning of the msb of control byte 1 is inverted, so that the controller always has to complement the auxiliary and rds data. 7.4.5. write dmx data s dev_write ($d4) a data_write ($68) a $50 a $00 a dmx1 a dmx0 dmx3 a dmx2 a dmx5 a dmx4 a dmx7 a dmx6 a p a fig. 7 ? 10: send 8 bytes to drp for dmx data decryption note: 8 dmx bytes (dmx0...dmx7) are received from the verifier ic. when writing these bytes to the drp, start with dmx1 before writing dmx0 etc. 7.4.6. write data into the d0-memory of the drp s dev_write ($d4) a data_write ($68) a $a0 a $00 a n3 n2 a n1 n0 a3 a2 a a1 a0 a d3 d2 a d1 d0 a $00 a $0 d4 a d3 d2 a d1 d0 a $00 a $0 d4 a p a repeat n times n3..n0 a3..a0 d4..d0 = number of words = start address in drp memory = data value count ?n? address ?a? data ?d? fig. 7 ? 11: write data to the d0 area writing data into memory areas may be used for control- ling the program execution (see section 8.) and for downloading purposes. before downloading, it is recom- mended to freeze the program execution. otherwise, the internal program may override the downloaded val- ues instantly. ? writing data into undocumented memory areas may corrupt the execution of the internal program.
advance information drp 3510a 29 micronas 7.4.7. write data into the d1-memory of the drp s dev_write ($d4) a data_write ($68) a $b0 a $00 a n3 n2 a n1 n0 a3 a2 a a1 a0 a d3 d2 a d1 d0 a $00 a $0 d4 a d3 d2 a d1 d0 a $00 a $0 d4 a p a repeat n times n3..n0 a3..a0 d4..d0 = number of words = start address in drp memory = data value fig. 7 ? 12: write data to the d1 area count ? n ? address ? a ? data ? d ? writing data into memory areas may be used for control- ling the program execution (see section 8.) and for downloading purposes. before downloading, it is recom- mended to freeze the program execution. otherwise, the internal program may override the downloaded val- ues instantly. ? writing data into undocumented memory areas may corrupt the execution of the internal program. 7.4.8. read data from the d0-memory of the drp s dev_write ($d4) a data_write ($68) a $e0 a $00 a n3 n2 a n1 n0 a3 a2 a a1 a0 a d3 d2 a d1 d0 a $00 a $0 d4 a d3 d2 a d1 d0 a $00 a $0 d4 nak p repeat for n data values n3..n0 a3..a0 d4..d0 = number of words = start address in drp memory = data value count ? n ? address ? a ? data ? d ? 2. get data s dev_write ($d4) a data_read ($69) a dev_read ($d5) 1. send command a p fig. 7 ? 13: read 20-bit data from the d0-memory of the drp a s
advance information drp 3510a 30 micronas 7.4.9. read data from the d1-memory of the drp s dev_write ($d4) a data_write ($68) a $f0 a $00 a n3 n2 a n1 n0 a3 a2 a a1 a0 a d3 d2 a d1 d0 a $00 a $0 d4 a d3 d2 a d1 d0 a $00 a $0 d4 nak p a repeat for n data values count ? n ? address ? a ? data ? d ? 2. get data s dev_write ($d4) a data_read ($69) a dev_read ($d5) 1. send command a p fig. 7 ? 14: read 20-bit data from the d1-memory of the drp s n3..n0 a3..a0 d4..d0 = number of words = start address in drp memory = data value 7.4.10. freeze s dev_write ($d4) a data_write ($68) a $00 a $00 a p fig. 7 ? 15: the freeze command should be executed before download of the new code to avoid noise signals at the output interfaces. before using the freeze command, it is recommended to mute the output. 7.4.11. the run command s dev_write ($d4) a data_write ($68) a a3 a2 a a1 a0 a p fig. 7 ? 16: the run command starts the execution at the program address a = (a3,a2,a1,a0).
advance information drp 3510a 31 micronas 8. internal registers and memory areas the following section describes internal registers and memory areas, that are accessible by the controller, in order to control or watch the internal operation of the drp. 8.1. default read (index and status) if a value is read from the drp without a previously given command, the 16-bit index and status value is returned by default. the index value can be used in a polling loop to synchronize the system controller with the transmitted layer 2 frame. the lower byte of the index/status always contains an odd number (if the drp is decoding) and is incremented by 2 after each update of the adr-data block. the upper byte indicates the status of the decoder as described in table 8 ? 1. 8.2. digital volume and channel mapping (write) four memory cells in the d1 area are used to control the digital volume of the drp output lines. these memory cells simply keep coefficients the stereo input signals are multiplied with. these coefficients are represented in a 20-bit fixed point notation (e.g. $80000 = ? 1.0 or $20000 = 0.25.) in order to achieve the corresponding fixed point value, divide the hex-value read from a regis- ter by 524288 = $80000. the 4 coefficients are located in the memory cells. this mapping may be used for vol- ume control, channel mapping, and for special stereo bandwidth effects. the default coefficients are negative in order to compensate a previous signal negation. fig. 8 ? 1: digital volume matrix ? 1 ? 1 ? 1 ? 1 ll rl rr lr left in right in left out right out table 8 ? 1: index and status word c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 m x x j w s f e i7 i6 i5 i4 i3 i2 i1 l bit number name value description 0 l 0 not counting, not decoding 0 l 1 synchronized and counting 1..7 i(1..7) 0..127 index (counts module 128), increment after each adr-data update 8 e 1 error in ancillary data field (probably corrected) 9 f 1 scale factor crc-error 10 s 1 carrier detect (does not work properly in e4 ? see bit0 for this purpose) 11 w 1 weak carrier (does not work properly in e4 ? see the agc register instead) 12 j 1 mpeg signal does not use 50 s preemphasis 13 x 0 14 x 0 15 m 1 mpeg layer 2 crc-error
advance information drp 3510a 32 micronas table 8 ? 2: digital volume matrix coefficients memory location: d1:$120 d1:$121 d1:$122 d1:$123 cell name ll lr rl rr default (stereo) ? 1.0 ($80000) 0 0 ? 1.0 ($80000) dual ch. (left) ? 1.0 ($80000) ? 1.0 ($80000) 0 0 dual ch. (right) 0 0 ? 1.0 ($80000) ? 1.0 ($80000) description maps left input to left output maps left input to right output maps right input to left output maps right input to right output 9. handling of the drp via internal registers the execution of the firmware adr-decoder in the drp can be monitored by reading internal registers. writing to registers allows a modification of the internal opera- tion, which may be useful for specific applications. all registers in the drp are accessible from the controller via i 2 c bus. the most useful registers that may be ac- cessed by the controller are listed in this paragraph. this allows detailed control and monitoring of many internal processes within the drp for any controller. writing into registers that are not listed below is possible, but it may cause unpredictable results or even a crash of the drp program. many of the readable register values may change very rapidly. smoothing, for example, by using a sliding average technique may be helpful. 9.1. the internal fixed point number format in many cases it is useful to convert the register or memory values ? v ? into a fixed number representation ? r ? . this is done easily by using the following algorithm: if (v 524288) { v = v ? 1048576; } r = v / 524288.0; vice versa, a real number ? r ? in the range from ? 1.0 to 1 ? 524287/524288 can be converted into the drp 20-bit two ? s complement representation ? v ? by using the algo- rithm: v = r*524288.0 + 0.5; if (v<0) { v = v + 1048576; }
advance information drp 3510a 33 micronas 9.2. main configuration register 96 (write) the main configuration register controls the operation of the adr decoder firmware. c 19 c 18 c 17 c 16 c 15 c 14 c 13 c 12 c 11 c 10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 fr g2 g1 g0 r r r r pd m1 r cp ai fs sp c j r q d bit number name value description 0 d 0 no decryption d 1 do dmx-decryption 1 q 0 18.432 mhz crystal is used (must be equal to pi0 setting) q 1 24.576 mhz crystal is used 2 r 0 reserved bits must always be set to ? 0 ? 3 j 0 do digital deemphasis, if requested by mpeg l2-header j 1 no deemphasis 4 c 0 use sp bit to enable scalefactor protection c 1 use transmitted bit stream info to enable scalefactor protection 5 sp 0 if (c=0), disable scalefactor protection sp 1 if (c=0), always enable scalefactor protection 6 fs 0 set fsi automatically (see section 11.3.) fs 1 disable setting fsi (fsi is low) 7 ai 0 default ancillary data handling (adr: deinterleaving, l2: no deinterl.) ai 1 invert default ancillary data handling (adr: no deinterl., l2: deinterl.) 8 cp 0 use copy protection setting of mpeg bit stream cp 1 force copy prohibited (recording the program is allowed, not copying) 9 r 0 reserved bits must always be set to ? 0 ? 10 m1 0 enable outputs m1 1 mute all outputs 11 pd 0 pio used for crc and fsi signals pd 1 disable fsi and crc and send undecoded l2-bit stream to pio 12...15 r 0 reserved bits must always be set to ? 0 ?
advance information drp 3510a 34 micronas description value name bit number 18, 17, 16 g2 g1 g0 gain adjustment for the incoming adr-data stream g2 g1 g0 100 101 110 111 000 001 010 011 ? 24 db ? 18 db ? 12 db ? 6 db 0 db (default value) +6 db +12 db +18 db 19 fr 1 force a restart (similar to a ? soft-reset ? ) 9.3. agc register 115 (read) the drp automatic gain control can be watched by reading the agc register (115). the agc value indi- cates if the gain of the single adr-carrier coming from the msp has a sufficient value. for proper operation, the agc value should be somewhere between $a0000 (= ? 0.75 ) and $e0000 (= ? 0.25). if the agc value is constantly showing $80000, the agc is out of its control range. this indicates that the video carrier of the msp input signal is not suppressed sufficiently or that the if input signal does not have a sufficient level. if the value is too small, the drp input gain should be reduced by adjusting the bits g2, g1, g0 in the main configuration register. 9.4. viterbi min-distance register 210 (read) the viterbi min-distance register content gives informa- tion about the bit error rate of the decoded signal. a smoothing of subsequent viterbi distance values will sta- bilize the result. if the viterbi min-distance is less than 5000, the channel quality is excellent. larger values in- dicate worse signal quality. bit errors can be expected, if the mean value of the viterbi min-distance exceeds 5300 . the value given by the viterbi min-distance regis- ter is only valid if the agc is working properly (see sec- tion 9.3.). the agc register value should not be at its li- mitation at $8000 . 9.5. clock-deviation register 244 (read, write) the clock deviation register holds a value that indicates the clock deviation of the drp-clock, which is set by the timing recovery algorithm with respect to the crystal ref- erence. if this value is set to ? 0 ? , the drp-clock exactly mirrors the xti (crystal) clock. a negative value indi- cates that the drp-clock is slower, a positive clock indi- cates a higher internal clock frequency. the output clock frequency can be derived from the clock-deviation regis- ter value by the following formula, where f stands for the fixed point representation of the clock deviation register content. f c = (39936 + 37.1613* f ) khz for f q = 18.432 mhz; ? 1.0 < f <+1.0 f c = (36684 + 33.0323* f ) khz for f q = 24.576 mhz; ? 1.0 < f <+1.0 9.6. timing recovery control register 168 (write) if the drp is running with an 18.432 mhz clock, the crys- tal may be omitted, and the aud_cl_out (signal of the msp, which is a 18.432 mhz clock) may be connected via 10 nf with the xti input signal of the drp. however, this mode of operation does affect the timing recovery of the system, which now has different behavior than using a separate crystal for the drp. in order to avoid an insta- ble timing recovery, the value $200 has to be written into the register 168 after each reset of the drp. 9.7. sp/dif configuration register 83 (write) the sp/dif configuration register sp0c can be used to disable the sp/dif output for special copy protection. this is done by writing the value $80 into this register. the only way of enabling the sp/dif output again, is a reset. 9.8. sdo0 configuration register 67 (write) this sdo0 configuration register can be used to control the format of the outgoing i 2 s signal. for some dacs, it is necessary to delay the data values by one clock vs. the wordstrobe signal. this can be achieved by writing the value $821 into this register (default content of the register $21).
advance information drp 3510a 35 micronas 9.9. so0auxa register 69 (write) the 12 lsbs of the register content of this register are placed into the 12 trailing bits of the left word of the i 2 s data stream. these bits can be used to send control in- formation to some dacs. 9.10. so0auxb register 70 (write) the 12 lsbs of the register content of this register are placed into the 12 trailing bits of the right word of the i 2 s data stream. these bits can be used to send control in- formation to some dacs. 9.11. sdi1 input configuration register 187 (write) for layer 2 decoding, some applications do generate an inverted clock signal with respect to the data. the inver- sion can be compensated by writing the value $1004 into this register. 9.12. sdi1 input selection register 79 (write) switching between the standard sdi1 input (which is the default) and the alternative sdi1* input is possible. the alternative input is selected by writing a ? 2 ? into this regis- ter. writing a ? 0 ? into the register will reset the input to the sdi1 lines. 9.13. actual mpeg header register 117 (read) register 117 contains a mirror of the actual mpeg head- er that has been read out from the incoming bit stream. table 9 ? 1: mpeg status bits bit number name comment 19 id always 1 18, 17 layer 10 = layer 2 16 protection bit 0 = crc protection included 1 = no crc protection included 15, 14, 13, 12 bit rate index 1010 for 192 kbit/s 11, 10 sampling frequency 01 = 48 khz 9 padding bit only for 44.1 khz f s 8 private bit for private use 7, 6 mode 00 = stereo, 01 = joint stereo, 10 = dual ? , 11 = single channel 5, 4 mode extension controls bit allocation for subbands 3 copyright 0 = no, 1 = copyright protected 2 original/copy 0: copy, 1: original 1, 0 emphasis should be 00 (no preemphasis) or 01 (50/15 s)
advance information drp 3510a 36 micronas 10. downloading of programs alternative software modules can be downloaded to the drp. the downloaded programs are either available by micronas or they can be developed by using the micro- nas masc 3500 software development package. the download can easily be done via the i 2 c bus. thus, addi- tional functionality may be added to the drp even if kept in the original adr-application. download modules are or will be available for: ? i 2 s to sp/dif conversion ? test signal generation ? dolby prologic ? panorama sound ? concert hall effects the download procedure is done the following way: 1. mute the audio outputs 2. freeze the operation 3. download the new program into the data memory 4. start the new program with the ? run ? command at the start address of the downloaded program now, the drp executes the new program. in order to switch back to normal operation, a simple ? reset ? is suffi- cient. after downloading, the original adr or mpeg software will not be disabled in the new program. tables and subroutines of the firmware are still available and executable. 0.75 kword of program code and 1.25 kword of data can be downloaded.
advance information drp 3510a 37 micronas 11. application recommendations 11.1. msp 3400c parameter setting for msp related parameters, please refer to the msp data sheet. 11.1.1. input gain and differences between the msp 3400c versions c6 and c7 for new development of adr receivers, the msp 3400c-c7 or later versions are recommended. this version includes an additional gain factor in the adr bus interface output to the drp, to enable optimal signal resolution also with adr stations in ? full trans- ponder mode ? . in ? full transponder mode ? , the frequency band normal- ly used for video transmission is used by adr carriers. with such signals, the level of one adr carrier is much lower than with a tv program with, for example, 5 sound carriers. note: the msp 3400c-c7 and later versions are compatible to the msp 3410d, regarding the adr- mode. if the msp 3400c-c7 or later versions, or the msp 3410d are used, together with the drp 3510a/e4 or later versions, the msp agc gain reference should be set to the value 20 dec (instead of 40 dec with the c6 version). with this, clipping at the msp input is avoided, especially with multi sound carrier programs. normally, the clipping of the msp input will cause no problems with adr syn- chronization but will reduce the viterbi distance value. all other settings remain as with the msp 3400c-c6 (see table 11 ? 1). together with these settings, it is recommended for the msp 3400c-c7, to limit the overall composite if input signal of the msp to a peak-to-peak level of about 0.7 vpp. it is recommended that the controller software check the msp version registers to set the msp agc gain refer- ence according to the msp version (see table 11 ? 2). this version check can be done by reading product and rom code only. the msp agc reference gain is set to 20 dec if the prod- uct code is ? 0 ? and the the rom code is smaller than ? 7 ? . table 11 ? 1: gain settings address meaning with msp 3400c-c6 with msp 3400c-c7 and msp 3410d 1) msp ad_cv[6:1] agc gain reference 40 dec 20 dec msp ad_cv[7] agc on/off 1 = on 1 = on msp ad_cv[9] carrier mute 0 = off 0 = off msp mode_reg[12] fir filter gain 0 = + 6 db 0 = + 6 db drp 3510a/e4... register 96[18...16] gain adjust 0 = 0 db 0 = 0 db 1) and all later versions table 11 ? 2: version codes version code address value for msp 3400c-c6 value for msp 3400c-c7 value for msp 3410d hardware 1e hex high byte 3 3 1 major revision 1e hex low byte 3 3 4 product 1f hex high byte 0 0 10 dec rom 1f hex low byte 6 7 34 dec
advance information drp 3510a 38 micronas 11.1.2. mode register table 11 ? 3: control word ? mode_reg ? : all bits are ? 0 ? after power-on-reset, settings for adr mode bit function comment definition recom- mendation for adr mode [0] dma_sync 1) synchronization to dma 0 : off 1 : on 0 [1] dctr_tri digital control out 0/1 tristate 0 : active 1 : tristate 1/0 [2] i2s_tri i 2 s outputs tristate (i2s_cl, i2s_ws, i2s_da_out) 0 : active 1 : tristate 0 [3] i 2 s mode 1) master/slave mode of the i 2 s bus 0 : master 1 : slave 1 (slave) [4] i 2 s_ws mode ws due to the sony or philips-format 0 : sony 1 : philips 0 (sony) [5] audio_cl_out switch audio_clock_output to tristate 0 : on 1 : tristate 0 (if used) [6] not used must be 0 0 [7] fm1 fm2 mspc-channel 1 mode 1 [8] am mspc-channel 1/2 mode 0 : fm 1 : am 0 [9] hdev high deviation mode (channel matrix must be sound a ) 0 : normal mode 1 : high deviation mode 0 [10] not used must be 1 1 [11] s-bus mode 2) mode of pins s_cl and s_id 0 : tristate 1 : active 1 [12] fm2 fir filter gain (fm2 = ch1) 0 : gain = 6 db 1 : gain = 0 db 0 (+ 6 db) [13] fm2 fir filter coeff. set (fm2 = ch1) 0 : use fir_reg_1 1 : use fir_reg_2 0 [14] adr mode of adr interface 0 : normal mode 1 : adr mode 1 [15] reserved reserved must be 0 0 1) in case of synchronization to dma, no i 2 s-slave mode possible. in case of i 2 s-slave mode, no synchronization to dma allowed. i 2 s-slave mode dominates. 2) the normal operation mode is ? tristate ? ; sbus is only used in conjunction with dma.
advance information drp 3510a 39 micronas 11.1.3. fir coefficients for fir_reg1 coefficient decimal hex c(0) 7 7 c(1) 23 17 c(2) 52 34 c(3) 84 54 c(4) 112 70 c(5) 127 7f 11.1.4. dco increment setting with sat carriers the following is an example of dco increment calcula- tion (fcarrier = 6200 khz): for the dco high part: dco_h = int [ 2*fcarrier [khz] / 9 ] = int [ 2*6200,0 / 9 ] = int [ 1377,77 ] = 1377 => dco_h = 561 hex for the dco low part: dco_l = 455 * int [ 2*fcarrier [khz] ? 9 x dco_h ] = 455 * int [ 12400,0 ? 12393 ] = 455 * 7 = 3185 => dco_l = c71 hex table 11 ? 4: dco increment settings frq. mhz dco_hi (hex) dco_lo 6.120 6.300 6.480 6.660 6.840 550 578 5a0 5c8 5f0 0 0 0 0 0 7.380 7.560 7.740 7.920 668 690 6b8 6e0 0 0 0 0 8.100 8.280 8.460 708 730 758 0 0 0 11.2. pure adr music decoding the drp processor always tries to synchronize itself to an incoming adr data stream as it is generated by the msp. as soon as the synchronization is done and a frame has been decoded correctly, the fsi signal (or the counting of the index value) indicates that the ic is de- coding properly and the corresponding status bits are set. without any additional adjustments from the controller, the serial outputs sdo0, sdo1, and sp/dif will gener- ate the digital music bit stream at 48, 32, and 48 khz sampling frequency. for the elementary free to air adr music decoding op- eration, no additional adjustments have to be done. 11.3. receiving the adr data the drp 3510a is controlled completely by the use of a controller with an i 2 c interface. the drp i 2 c interface is of the slave type. in addition to the i 2 c-device address, subaddresses are used. there are two ways of communicating with the drp: 1. reading or writing internal drp registers via special register read/write commands. this may be useful for configuration purposes, e.g. for configuring an interface or for reading the status register of the receiver (crc-check error, dmx, no input avail- able, ...). 2. reading the adr status and data block. the adr-status and data block consist of a16-bit status word plus 9 words 16-bit (adr ancillary data) as docu- mented in the astra/dmx specification. the error correction for these data values is already performed within the drp. in order to read out these values, the controller has to send a specific i 2 c command to the drp, which initiates the drp to send these 10 data val- ues. there are two ways to check whether a new data block is available. in the normal mode (pio used for fsi, fsi automatic), the fsi is low when new data are avail- able. after readout by the controller, but at the latest be- fore these data become invalid, the fsi becomes high. otherwise, the incremented index of the 16-bit status word is to check. the fsi signal (see section 3.) or the incremented index of the 16-bit status word may be used to check whether a new data block is available.
advance information drp 3510a 40 micronas 11.4. receiving fm / tv sound with msp when the msp is configured for receiving analog fm/tv sound, the internal pll of the drp has to be switched off. this is to prevent frequency deviation caused by the drp timing recovery, which tries to receive adr further on. there are two options available. first, is to use the download program i 2 s to sp/dif. this gives the advan- tage of having the fm/tv sound at the digital interface and at the 48 khz dac as well. the second option is to configure the msp as master and set its i 2 s-bus to tris- tate. this can be done with a single i 2 c-command (see data sheet of msp). this latter option will not work in the 24.576 mhz single crystal mode (8.3). the following download programs are available: src_e4b.mas: msp fm sound via i 2 s (32 khz at sdi1) to: ? spdif output (48 khz) ? hq dac output (sdo0 with 48 khz) ? feed back to the drp i 2 s out (sdo1 with 32 khz) spdif_e4.mas : msp fm sound via i 2 s (32 khz at sdi1) to: ? spdif output (32 khz) ? hq dac output (sdo0 with 32 khz) ? feed back to the drp i 2 s out (sdo1 with 32 khz) 11.5. receiving of adr once receiving adr, the content of the clock-deviation register (see 9.5.) is associated with the deviation of the crystal. it is helpful and will speed up the synchronization to re-initialize this register after changing the adr-sta- tion with this value. if the drp is not receiving adr with- in more than 10 seconds (no carrier, device not con- nected with lnc, ...) it is necessary to re-initialize the clock-deviation register as well. this can be detected by watching the l-bit of the index register (see section 8.1.).
advance information drp 3510a 41 micronas 11.6. typical adr application circuit (drp application with 24 mhz single crystal mode) d a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 +5 v dig. 10 uf 100 nf 18 pf 10 uf 100 nf 100 nf 10 uf 24.576 mhz fsiq crce fsiq high quality 48 khz dac 10 nf 56 pf avss xti avdd xto te nc. pi0 pi1 pi2 pi3 so1c so1i so1d si1c si1i si1d vss vdd spdif so0c so0i clko porq i2cc i2cd vdd vss nc eodq prtrq prtwq pcsq pi18 (crce) pi17 pi16 (si1c*) nc pi15 (si1i*) pi14 (si1d*) pi13 pi12 so0d pi19 (fsiq) pr drp 3510a msp 3400c xtal_in main, aux out 18.432 mhz sat tuner scart in/out 61 resetq 21 7645681 3 9 8 xtal_out 20 nc. 100 nf 48 khz +5 v 25 i 2 s interface adr-bus interface if a/d a/d, d/a d/a crystal oscillator analog +5 v dig. +5 v dig. +5 v dig. reset from ccu 18 pf i 2 c bus i 2 c bus 10 k 10 k 10 k 10 k 390 ? 10 k 10 k
advance information drp 3510a 42 micronas 11.7. typical adr application circuit (drp application with 18 mhz dual crystal mode) d a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 +5 v dig. 10 uf 100 nf 18 pf 10 uf 100 nf 100 nf 10 uf fsiq crce fsiq high quality 48 khz dac 10 nf 56 pf avss xti avdd xto te nc. pi0 pi1 pi2 pi3 so1c so1i so1d si1c si1i si1d vss vdd spdif so0c so0i clko porq i2cc i2cd vdd vss nc eodq prtrq prtwq pcsq pi18 (crce) pi17 pi16 (si1c*) nc pi15 (si1i*) pi14 (si1d*) pi13 pi12 so0d pi19 (fsiq) pr drp 3510a msp 3400c xtal_in main, aux out sat tuner scart in/out 61 resetq 21 7645681 3 9 8 xtal_out 20 nc. 100 nf 48 khz +5 v 25 i 2 s interface adr-bus interface if a/d a/d, d/a d/a crystal oscillator analog +5 v dig. +5 v dig. reset from ccu 18 pf i 2 c bus i 2 c bus 10 k 10 k 10 k 10 k 390 ? 10 k 10 k aud_cl_out 18 18.432 mhz 3.3 pf 3.3 pf 18.432 mhz 18.432 mhz
advance information drp 3510a 43 micronas 12. timing diagrams 12.1. pio timing t pic h l pr prtwq prtrq pi[19:0] h l h l h l h l eodq t pic controller reads from drp: pio dma mode t piset t pie t pihold h l t pic h l h l h l h l t pic controller writes to drp: t piset t pie t pihold fig. 12 ? 1: pio timing 12.2. fsi timing h l pi19 (fsi ) t fsiv fig. 12 ? 2: fsi-timing t fsip
advance information drp 3510a 44 micronas 12.3. sdi timing h l h l h l t siids t siiss t siiss t siidh t siish sclk li sdin t siclk t siilia fig. 12 ? 3: sdi timing 12.4. sdo timing h l h l h l t soodc t soiss t soiss sclk li sdout t soclk fig. 12 ? 4: sdo timing 12.5. spdif timing h l spdif t spclk sync impulse data 0.5*t spclk 1.5*t spclk fig. 12 ? 5: spdif timing
advance information drp 3510a 45 micronas 12.6. recommended power up sequence 12.6.1. power up sequence for dual crystal modes vdd porq fig. 12 ? 6: recommended power up sequence (dual crystal modes) 2.3 v 4.75 v > 20 ms 12.6.2. power up sequence for 18.432 mhz single crystal mode vdd porq fig. 12 ? 7: recommended power up sequence (18 mhz single crystal mode) 2.3 v 4.75 v > 5 ms 12.6.3. power up sequence for 24.576 mhz single crystal mode vdd i 2 c-reset at msp porq fig. 12 ? 8: recommended power up sequence (24 mhz single crystal mode) h l 2.3 v 4.75 v >2 ms > 20 ms
advance information drp 3510a 46 micronas 13. drp 3510a version history version d3 (05.03.96) improvements and new features: ? single crystal option ? adjustable gain ? spdif tristate switchable ? pio-read mode ? get adr data modified (with offset) known bugs/status: ? fsi will not set (workaround available) ? inverted sdo-clock delay (workaround available) ? l2 pll does not work ? layer 2 decoder does not synchronize to all bitstreams with fs = 44, 1 khz version e4 (12.06.96) improvements and new features: ? fast synchronization, better c/n ? setup of sample rate converter (to msp) improved ? sp/dif holds synchronization even in ? channel hop- ping ? ?? force restart ? (bit 19 at main configuration register) works at anytime ? delay bit removed from fsi off-bit added to main con- figuration register ? sdo0 wordstrobe inverted (according to the da conv- terters) ? download program i 2 s to spdif with sample rate con- version to 48 khz available ? layer 2 decoder: 44.1 khz bug fixed, pll works known bugs/status: ? status: ? weak carrier ? does not work properly (worka- round available) ? status: ? carrier detect ? does not work properly (worka- round available ? pio-mode with disturbances
advance information drp 3510a 47 micronas
advance information drp 3510a 48 micronas 14. data sheet history 1. advance information: ? drp 3510a digital radio processor ? , jan. 16, 1997, 6251-410-1ai. first release of the advance information. micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-410-1ai all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirma- tion form; the same applies to orders based on development samples delivered. by this publication, micronas gmbh does not assume re- sponsibility for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh.

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